Surface micromachining process for manufacturing electro-acoustic transducers, particularly ultrasonic transducers, obtained transducers and intermediate products

ABSTRACT

A surface micromachining process for manufacturing Electro-acoustic transducers, particularly ultrasonic transducers, the transducers comprising a silicon semiconductor substrate ( 1 ), on an upper surface of which one or more membranes ( 18 ) of resilient materials are supported by a structural layer ( 11 ) of insulating material, rigidly connected to the semiconductor substrate ( 1 ), the resilient material having a Young&#39;s modulus not lower than 50 GPa, the membranes ( 18 ) being metallised, the transducers including one or more lower electrodes ( 23, 25 ), rigidly connected to the semiconductor substrate. The process is characterised in that the structural layer ( 11 ) includes silicon monoxide. The invention further relates to an Electro-acoustic transducer, particularly an ultrasonic transducer, characterised in that the insulating material of the structural layer ( 11 ) is silicon monoxide. The invention also relates to an intermediate product for utilisation in the process for realising Electro-acoustic transducers, particularly ultrasonic transducers.

This invention relates to a surface micromechanical process formanufacturing Electro-acoustic transducers, particularly ultrasonictransducers, which enables an extremely high design flexibility to beachieved, in respect of the geometry and of the electrical andmechanical features of the device, as well as the maximum compatibilitywith the integration of control electronics directly on a substrateincorporating the transducers.

Furthermore, this invention relates to an Electro-acoustic transducermanufactured by the above process and to an intermediate product of saidprocess.

It is known that the ultrasonic electrostatic capacitive transducersrepresent a suitable alternative to the piezoelectric transducers, sincethey are a solution of the problem of the 5 magnitudo order of mismatchwith the air acoustical impedance. Such electrostatical capacitivetransducers, also designated as cMUT (Capacitive MicromachinedUltrasonic Transducers) are manufactured by planar surfacemicromanufacturing techniques on silicon, thereby offering thepossibility to integrate the control electronics on the same chip.

The above mentioned cMUT devices are specifically used for ecographicimage acquisition, even if their application is not exclusivelyrestricted to such field. In particular, these transducers enable tocarry out multi-frequency ecographic scanning as well as the acquisitionof three-dimensional images in real time, with a scarcely invasiveexamination, such as an acoustic examination.

The micromanufactured capacitive transducers were firstly realised in1998 at the Stanford University, California, where a search teamdirected by Khuri Yakub has been working in this field for about tenyears.

In particular, the relevant prior art includes U.S. Pat. No. 5,619,476,upon which the preamble portions of claims 1, 47 and 60 are based,disclosing three processes for manufacturing corresponding transducers.

The first process provides for a silicon substrate upon which athermally grown sacrificial layer of silicon dioxide is realised. Inparticular, the thermal oxidation of the silicon broadly occurs attemperatures in the range of 900° C. to 1200° C. A layer of siliconnitride is then deposited on said sacrificial layer by a low pressurechemical vapour deposition procedure or LPCVD procedure, which isgenerally carried out at temperatures in the range of 700° C. to 900° C.Lastly, the sacrificial layer is partially removed by an etchingoperation which should be carefully timed in order to control themembrane size. At the end of the process, one obtains transducerscomprising membranes of silicon nitride supported by portions of thesilicon dioxide sacrificial layer that have not been removed by theetching operation.

A second process provides for realising by a deposition proceduregrooves of silicon nitride aimed at defining the borders of the silicondioxide sacrificial layer areas, in order both to realise membranes ofarbitrary shapes and to make the chemical etch timing less critical. Atthe end of the process, one obtains transducers comprising membranes ofsilicon nitride rigidly supported by the silicon nitride grooves. Inparticular, since the subsequently deposited layers of silicon nitrideraise adhesion problems when the deposition is carried out at lowtemperature, it is apparent that the concerned silicon nitride should bedeposited also in this second process by means of a LPCVD procedure athigh temperature.

A third process provides for a glass substrate upon which a polyamidesacrificial layer is realised. A layer of silicon nitride is depositedupon said sacrificial layer by means of a plasma enhanced chemicalvapour deposition on PECVD procedure, which necessarily takes place atlow temperatures, in the range of 200° C. to 400° C., in order not toburn the polyamide. Lastly, the sacrificial layer in partially removedby means of a carefully timed chemical etching operation aimed atcontrolling the membrane size. At the end of the process, one obtainstransducers comprising silicon nitride membranes supported by portionsof the polyamide sacrificial layer not removed by said etchingoperation. The known prior art also includes document 1. Ladabaum, X.Jin, H. T. Soh, A. Atalar and B. T. Khuri Yakub, “Surface MicromachinedCapacitive Ultrasonic Transducers”, IEEE Trans. Ultrason. Ferroelect.Freq. Contr., Vol 45, pp. 678–690, May 1998, that, in the assumption ofa theoretical model representing the Electro-acoustic behaviour of anultrasonic transducer, discloses a manufacturing process similar to theprocess described in U.S. Pat. No. 5,619,476.

The known prior art further includes U.S. Pat. No. 5,870,351 thatdiscloses a process for manufacturing a large band ultrasonic transducercomprising a plurality of membranes of different geometric shapeselectrically connected with one another. The disclosed manufacturingprocess is similar to the first process described in U.S. Pat. No.5,619,476, with the possible variation in which a plastic material ringis provided for limitation of the sacrificial layer areas correspondingto the membranes.

Further included in the known prior art is U.S. Pat. No. 5,894,452disclosing a process for manufacturing an ultrasonic transducer adaptedto operate in submerged condition in a fluid. The manufacturing processas disclosed is again analogous to the first process described in U.S.Pat. No. 5,619,476, with addition of a further step aimed at sealing thevias by CVD deposition of a further silicon nitride layer. In thisprocess, the size of the concerned vias appears to be particularlycritic, in order to guarantee that no silicon nitride is introducedunder the membranes during the sealing step.

The known prior art also includes U.S. Pat. No. 5,982,709 that disclosesa process for manufacturing an ultrasonic transducer wherein themembranes and their supports are formed during the same silicon nitridedeposition and wherein the material deposited for sealing the vias isprevented from reaching the area underlying the membranes by definingthe vias only in correspondence to tanks and to complex connectionchannels between the vias and the underlying areas of the membranes.This manufacturing process is analogous to the second process describedin U.S. Pat. No. 5,619,476, with the possible variation of a polysiliconsacrificial layer, aimed at increasing the selectivity of the etchingsolution. Also in this process, the size of the vias appears to beparticularly critic.

Lastly, the known prior art also includes PCT Application No. WO00/72631, that disclosed an acoustic transducer and a process formanufacturing it similar to the previously mentioned ones, in which thelower metallisation is realised in the chambers formed just under themembranes. The described manufacturing process uses aluminium or siliconoxide deposited at low temperature as sacrificial materials. Thematerials utilised for making the electrodes are aluminium or copper ortungsten having low resistivity.

The processes disclosed in the prior art, particularly in U.S. Pat. No.5,619,476 have some drawbacks.

In the first place, the sacrificial layer, the membranes and themembrane supports are realised with only two different materials. Thismakes the selection of the process parameters and of the chemicaletching solutions particularly critic for the obtainment of highselectivities, in order to control the geometry and the electrical andmechanical features of the process. Obviously, these critical aspects ofthe process make the latter particularly complex and expensive.

Furthermore, many processing steps are carried out at high temperatures,no lower than 600–700° C., thereby making the selection and the controlof the process parameter additionally critic and reducing compatibilityof the concerned process with the integration of control electronics onthe same substrate on which the transducers are realised.

In addition, the utilised materials and the processing temperaturescause an irregular planarity of the manufactured devices, therebycausing the establishment of significant parasitic capacitances in thetransducers themselves, which, in turn, jeopardise their correctoperation modes.

Furthermore, the third process as proposed by the U.S. Pat. No.5,619,476 appears to be quite inefficient, due to the fact thatpolyamide is quite unsuitable as a support layer. In fact, this materialhas a quite low Young's modulus and therefore, a polyamide support forthe concerned membranes would track the vibrations thereof, by absorbingthem and generating beat effects. In addition, the intrinsic compressionstress of the silicon nitride membranes deposited by a PECVD depositionprocedure at low temperature appears to be extremely high, therebyfurther making the concerned membranes highly inefficient, while themembranes themselves should have a small intrinsic tensile stress. Onthe other hand, should it be desired to use silicon nitride layers assupports of the membranes (and possibly as grooves of the sacrificiallayer), a further drawback would be encountered caused by the lowadhesion of the subsequently deposited membranes of silicon nitride; infact, the requirement to have high temperatures in order to obtain agood adhesion could not be fulfilled because, in stead, low processtemperatures are necessarily required in order to prevent the polyamidefrom burning. In effect, the just above discussed problems in respect ofthe third process have resulted into elimination of such approach fromall above mentioned known prior art subsequent to U.S. Pat. No.5,619,476.

Also in PCT Application No. WO/0072631 the sacrificial layers ofaluminium or silicon oxide deposited at low temperature raise thedrawbacks due to the poor selectivity of the chemical etching operationsneeded for their elimination, thereby making the manufacturing processcritic and, consequently, complex and expensive.

Furthermore, the residual mechanical stress level of the membranes of atransducer manufactured by the above discussed known processes isparticularly high and hardly controllable, since it noticeably dependson the proportion between silicone (SiH₄) and ammonia (NH₃) and anywayit cannot be handled in arbitrary manner.

Lastly, the membranes have high gradients of mechanical stress, due tothe fact that the membranes themselves have apertures or vias in thesilicon nitride layer, as needed to permit the sacrificial layer to beetched. U.S. Pat. No. 5,982,709 proposes a solution to overcome suchproblem by means of a complex and expensive definition of patternscomprising grooves and intricate channels.

It is an object of this invention, therefore, to provide a surfacemicromechanical process for manufacturing Electro-acoustic transducerswhich enable to achieve in simple, inexpensive and reliable way a highdesign flexibility, in respect of the geometry as well as the electricaland mechanical features of the device, together within the maximumcompatibility with the integration of control electronics directly onthe same substrate incorporating the transducers.

Another object of this invention is to provide a process of the abovekind to maximise the planarity of manufactured transducers and to enablea dramatic reduction of the parasitic capacitances to be achieved insuch devices.

Such objects are realised by using silicon monoxide deposited at lowtemperature, as a structural support layer for the membranes.

A further object of this inventions to provide a process of the abovekind which enables a substantially arbitrary reduction to be obtained inthe residual mechanical stresses in the membranes of the manufacturedtransducers.

A still further object of this invention is to provide a process of theabove kind which enables a dramatic reduction of the mechanical stressgradients in the membranes as caused by presence of vias therein. It isspecific subject-matter of this invention to realise a surfacemicromachined process for manufacturing Electro-acoustic transducers,particularly ultrasonic transducers, said transducers comprising asilicon semiconductor substrate, on an upper surface of which one ormore membranes of resilient materials are supported by a structurallayer of insulating material, rigidly connected to said semiconductorsubstrate, said resilient material having a Young's modulus not lowerthan 50 GPa, said membranes (18) being metallised, said transducersincluding one or more lower electrodes, rigidly connected to saidsemiconductor substrate, the process comprising the following steps:

-   A. providing a silicon semiconductor substrate,-   B. realising an intermediate product comprising:    -   a sacrificial layer, and    -   a structural layer of insulating material,        rigidly connected to an upper surface of said silicon        semiconductor substrate, the surfaces of said sacrificial layer        and of said structural layer not in contact with said substrate        being substantially co-planar,-   C. depositing a layer of said resilient material on said sacrificial    layer and on said structural layer, and-   D. releasing said membranes of said resilient material by removing    said sacrificial layer from the product obtained according to said    step C.,    said process being characterised in that said structural layer    includes silicon monoxide.

Preferably according to this invention, all of the steps of the processare carried out at temperatures no higher than 600° C. and even morepreferably at temperatures no higher than 530° C.

Preferably according to this invention, said resilient material has avalue of the Young's modulus no lower than 100 GPa.

Even more preferably according to this invention, said resilientmaterial comprises silicon nitride.

According to this invention, said resilient material can comprisecrystalline silicon.

Preferably according to this invention, said sacrificial materialcomprises chromium.

Alternatively according to this invention, said sacrificial materialcomprises an organic polymer selected among the group comprisingpolyamides and polymers of benzocyclobutene and its derivatives,preferably polyamide and even more preferably N-methyl-2-pyrolidone.

According to this invention, said step D can comprise the followingsuccessively ordered sub-steps:

-   D.1 realising one or more apertures or vias on said layer of    resilient material, adapted to enable accessing the sacrificial    layer from outside, and-   D.2 thermally treating by annealing the product obtained according    to said step C.

Further according to this invention, during execution of said sub-stepD.2, the product obtained according to said step C is heated to atemperature in the range of 490° C. to 530° C.

Again according to this invention, said sub-step D.2 can be of aduration adapted to completely eliminate the organic polymer existing inthe product obtained according to said step C.

Still according to this invention, said step D can further comprise,indifferently before or after said sub-step D.1 or D.2, the followingsub-step:

-   D.3 chemically etching said sacrificial layer.

Still according to this invention, said sub-step D.3 can compriseimaging the product in a wet etching solution for etching chromium.

Alternatively according to this invention, said sub-step D.3 cancomprise imaging the product obtained according to said step C in asolution comprising sulphuric acid (H₂SO₄) and possibly hydrogenperoxide (H₂O₂), in which case said solution is a solution 7:3 ofsulphuric acid (H₂SO₄) and hydrogen peroxide (H₂O₂).

Further according to this invention, when said sub-step D.3 issubsequent to said sub-step D.2, said step D can further comprise, aftersaid sub-step D.3, the following sub-step:

-   D.4 thermally treating by annealing the product obtained according    to said step D.

Also according to this invention, during execution of said sub-step D.4,the product obtained according to said step C can be heated to atemperature in the range of 490° C. to 530° C.

Preferably according to this invention, the total duration of theannealing operation for the product obtained according to said step C isadapted to make the intrinsic compression stress of the membranes (18)no higher than 10 MPa.

Again according to this invention, the total duration of the annealingoperation for the product obtained according to said step C is adaptedto make the intrinsic tensile stress of the membranes comprised in therange of 10 MPa to 50 MPa.

Further according to this invention, said vias can be external to thelocations of said membranes and can be positioned at a distancetherefrom adapted to introduce substantially negligible stressgradients, said sacrificial layer comprising channels to connect thepositions of said vias to the locations of said membranes.

Still according to this invention, said step B can comprise thefollowing successively ordered sub-steps:

-   B.1 depositing a chromium comprising layer on said upper surface of    the semiconductor substrate,-   B.2 defining configurations or patterns in said chromium comprising    layer by realising cavities in said chromium comprising layer, and-   B.3 filling said cavities in said chromium comprising layer by    depositing silicon monoxide therein.

Alternatively according to this invention, said step B can comprise thefollowing successively ordered sub-steps:

-   B.1 applying a polyamide comprising layer upon said upper surface of    the semiconductor substrate,-   B.2 defining configurations or patterns in said layer polyamide    comprising layer by realising cavities (10) in said in said    polyamide comprising layer, and-   B.3 filling said cavities in said polyamide comprising layer by    depositing silicon monoxide therein.

Still according to this invention, during said sub-step B.3, the siliconmonoxide can be deposited by thermal evaporation.

Further according to this invention, said sub-step B.2 can comprise anoptical lithographic process performed on said chromium comprising layerby utilising a masking layer of photographically patterned opticalresist and a wet chemical etching of the chromium.

Alternatively according to this invention, said sub-step B.2 cancomprise a dry reactive ion etching (RIE) operation performed on saidpolyamide comprising layer by utilising a masking layer ofphotolithographically patterned optical resist.

Still according to this invention, said step B can further comprise,after said sub-step B.3, the following sub-steps:

-   B.4 chemically etching said silicon monoxide by utilising a wet    etching process,-   B.5 removing said optical resist.

Alternatively according to this invention, said step B can furthercomprise, after said sub-step B.3, the following sub-step:

-   B.4 removing the silicon monoxide deposited upon said optical resist    by means of a lift off process.

Still according to this invention, said sub-step B.4 can also comprisedissolving said optical resist by means of an acetone and ultrasounddissolving process.

Alternatively according to this invention, said step B can comprise thefollowing successively ordered sub-steps:

-   B.1 depositing a silicon monoxide comprising layer on said upper    surface of the semiconductor substrate,-   B.2 defining configurations or patterns in said silicon monoxide    comprising layer,-   B.3 applying a polyamide comprising layer upon said upper surface of    the semiconductor substrate, provided with silicon monoxide,-   B.4 performing a chemical-mechanical polishing operation adapted to    realise said intermediate product.

Still according to this invention, during said sub-step B.1, the siliconmonoxide can be deposited by thermal evaporation.

Further according to this invention, said sub-step B.2 can comprise adry reactive ion etching (RIE) operation performed on said siliconmonoxide comprising layer by utilizing a masking layer ofphotolithographically patterned optical resist.

Preferably according to this invention, during said step C, saidresilient material is deposited by a plasma enhanced chemical vapourdeposition process (PECVD).

Still according to this invention, said process can further comprise,after said step D, the following step:

-   E. closing said vias by    -   deposition of silicon monoxide adapted to fill up said vias,    -   optical lithography, and    -   RIE etching of the silicon monoxide deposited on said membranes.

Still according to this invention, during said step E, the siliconmonoxide can be deposited by thermal evaporation.

Further according to this invention, said process can also comprise,before said step B, the following step:

-   F. realising a lower electrode on the upper surface of the    semiconductor substrate in positions corresponding to each area in    which said membranes are realised during said step D.

Again according to this invention, said step F comprises the followingsub-steps:

-   F.1 depositing an insulating layer on the upper surface of the    semiconductor substrate,-   F.2 depositing a conductive layer upon said insulating layer,-   F.3 defining configurations or patterns in said conductive layer.

Again according to this invention, said insulating layer can comprisethermal silicon dioxide SiO₂, said conductive layer can compriseevaporation deposited chromium, and said sub-step F.3 can comprise anoptical lithographic process performed on said conductive layer byutilising a masking layer formed by a photolithographically patternedoptical resist and a chemical wet etching of the chromium.

Further according to this invention, said step F can further realise afilm for protection of said lower electrodes.

Still according to this invention, said protection film is realised bygrowing a film of silicon nitride SiN by means of a PECVD technique.

Alternatively according to this invention, said process can furthercomprise the following step:

-   F. realising one or more lower electrodes by metallisation of a    lower surface of said semiconductor substrate.

Again according to this invention, said process can further comprise thefollowing step:

-   G. metallising said membranes.

Preferably according to this invention, said silicon semiconductorsubstrate is a p-type doped silicon substrate having a resistivity nohigher than 1 Ω.cm, preferably no higher than 2 Ω.cm.

Still according to this invention, said silicon monoxide comprisingstructural layer has a thickness in the range of 100 nm to 1000 nm,preferably in the range of 400 nm to 600 nm, and said membranes of saidresilient material can have a thickness no higher than 1000 nm,preferably no higher than 600 nm.

It is further subject-matter of this invention the realisation of anElectro-acoustic transducer, particularly an ultrasonic transducer,comprising a silicon semiconductor substrate, on an upper surface ofwhich one or more membranes of resilient materials are supported by astructural layer of insulating material, rigidly connected to saidsemiconductor substrate, said resilient material having a Young'smodulus not lower than 50 GPa, said membranes being metallised, saidtransducer including one or more lower electrodes, rigidly connected tosaid semiconductor substrate, said transducer being characterised inthat said insulating material is silicon monoxide.

Preferably according to this invention, said resilient material has avalue of the Young's modulus no lower than 100 GPa.

Even more preferably according to this invention, said resilientmaterial comprises silicon nitride.

Further according to this invention, said resilient material cancomprise crystalline silicon.

Preferably according to this invention, the membranes of the transducerhave an intrinsic compression stress no higher than 10 MPa.

Still according to this invention, said membranes of the transducer havean intrinsic tensile stress in the range of 10 MPa to 50 MPa.

Again according to this invention, said structural layer of thetransducer can have a thickness in the range of 100 nm to 1000 nm,preferably in the range of 400 nm to 600 nm, and said membranes of thetransducer can have a thickness no higher than 1000 nm, preferably nohigher than 600 nm.

Preferably according to this invention, said one or more lowerelectrodes are realised on the upper surface of said semiconductorsubstrate in positions corresponding to each of said areas underlyingsaid membranes.

Further according to this invention, said transducer can furthercomprises an insulating layer, underlying said lower electrodes, on theupper surface of said semiconductor substrate.

Still according to this invention, said insulating layer can comprisesilicon dioxide SiO₂ and said conductive layer can comprise chromium.

Again according to this invention, said transducer can further comprisea film for protection of said lower electrodes.

Further according to this invention, said protection film can comprisesilicon nitride SiN.

Alternatively according to this invention, said one or more lowerelectrodes are realised by means of a metallised layer on said lowersurface of the semiconductor layer.

It is further subject-matter of this invention an intermediate productfor realising Electro-acoustic transducers, particularly ultrasonictransducers, comprising

-   -   a sacrificial layer, and    -   a structural layer of insulating material,        rigidly connected to an upper surface of said silicon        semiconductor substrate, the surfaces of said sacrificial layer        and of said structural layer not in contact with said substrate        being substantially co-planar, said intermediate product being        characterised in that said structural layer comprises silicon        monoxide.

Preferably according to this invention, said sacrificial layer compriseschromium.

Alternatively according to this invention, said sacrificial material cancomprise an organic polymer selected among the group comprisingpolyamides and polymers of benzocyclobutene and its derivatives.

Preferably according to this invention, said organic polymer comprisespolyamide.

Still according to this invention, said sacrificial layer and saidstructural layer have a thickness in the range of 100 nm to 1000 nm,preferably in the range of 400 nm to 600 nm.

Again according to this invention, said intermediate product can furthercomprise a layer of resilient material having a Young's modulus no lowerthan 50 GPa, superimposed on said sacrificial layer (8) and on saidstructural layer.

Preferably according to this invention, said resilient material of theintermediate product has a value of the Young's modulus no lower than100 GPa.

Even more preferably according to this invention, said resilientmaterial of the intermediate product comprises silicon nitride.

Further according to this invention, said resilient material of theintermediate product can comprise crystalline silicon.

Still according to this invention, said layer of resilient material canhave a thickness no higher than 1000 nm, preferably no higher than 600nm.

The process according to this invention is innovative both in respect ofthe utilised materials and in respect of the implemented step set. Thetechnologic process utilised a maximum temperature no higher than 600°C., thereby enabling an extremely high design flexibility to be obtainedtogether with the direct integration of control electronics on the chip.

During the process development, the inventors have addressed a number ofproblems. First of all, the implemented techniques and the conventionalmaterials employed therein did not enable a structurally integral deviceto be obtained. The transducer became useless due to detachment andbreakage of its structural layers, which were subject to high intrinsicstresses. Furthermore, all conventional materials as utilised thereindid not offer any possibility to apply highly selective chemical etchingprocedures.

The solution of such problems, therefore, enables mechanically validtransducers to be obtained. Use of a special polymer has beenintroduced, polyamide, in substitution for the more conventional siliconcompounds. In the second place, the analysis of the chemical-physicalcharacteristics of the materials and their reaction to thermaltreatments enabled to determine the necessary durations and temperaturesfor the obtainment of films, with moderate and not destructive stresses.Lastly, it has been possible to strenghten the structure by designing aspecial geometrical shape that, by avoiding a concentration of thestresses to restricted areas of the film, made it possible to uniformlydistribute such stresses thereby preventing any weakness point fromestablishing.

In summary, the utilised techniques and novel material made it possibleto realise a structurally integral device having all desired mechanicalproperties. The obtained device has been successfully tested both inrespect of the electrical impedance measurement and in respect of theacoustic signal measurement in reception-transmission.

The process according to this invention has been developed bysuccessfully experimenting the pre-patterning technique for effectivelycontrolling the geometry of the transducer components. In particular,the electrostatic cells were preliminarily shaped in order to achieve anoptimum control of the dimensional and geometric features of theindividual cells. Novel and not conventional materials never previouslyexploited in the micromanufacture field have been utilised in thisprocess. Particular relevance is to be attributed to utilisation of lowtemperature evaporate silicon monoxide as a structural layer to form theside supports of the membranes, also designated hereinafter as “rails”.In view of the low temperature deposition technique, it is perfectlycompatible with the photoresist as needed for the subsequent liftingremoval or simply lift off operation, as well as with the organicmaterial utilised as sacrificial layer. On the other hand, the lift offtechnique offers simplicity and unexpensiveness advantages in theprocess exploitation. The polyamide utilised as sacrificial layerenables an exceptional chemical etching selectivity to be obtained inrespect of the material by which the transducer is made, therebyallowing to maintain the characteristic properties of the structurallayers. The mechanical properties of the silicon nitride film grown by aPECVD technique appear to be easier to be controlled. A particulartechnique has been established to remove the sacrificial layer in ordernot to cause the adhesion of the structural layer to the substrate(stiction).

Electrical impedance measurements have been carried out on the sorealised devices and a mechanical resonance in the air at 5 MHz has beenevidenced.

In conclusion, the characteristics of the process according to thisinvention are the realisation of a pre-patterning procedures for thecavities, the utilisation of silicon monoxide to form the rails, theutilisation of a PECVD reactor for deposition of the layer that formsthe membranes and the utilisation of chromium or of a polymer, namely apolyamide, as a sacrificial layer, which enable to planarise the surfaceupon which the silicon nitride will be subsequently deposited. By thesefeatures the presence of a not planar membrane structure, withconsequent easy breakage at the edges, are avoided. The pre-patterningstep is very important because if offers a valid stoppage to thechemical attack, or etch stop, on releasing the membranes and thechromium or the polymer are easily workable by the usualmicromanufacturing techniques on silicon. The high process versatilityis made possible in view of the fact the chemical etch utilised forremoval of the chromium or the polymer, offers a 100% selectivity inrespect of the utilised materials, such as the silicon nitride, thesilicon monoxide and the silicon itself. By this procedure, thematerials by which the transducer will be effectively made are in no waydeteriorated, thereby maintaining all their quality levels in respect ofstrength and density. The apertures or vias for etching the sacrificiallayer are realised by means of a lithographic process and are optimisedso as to be subsequently closed in the final stage again by means of alithographic process.

A close study of the stresses under which the silicon nitride is grownin the PECVD reactor and thermal treatments have been designed tocontrol such stresses, in order to realise membranes having the desiredmechanical properties to optimise the performances of the transducer.The analysis of the stress has further been performed by consideringthat silicon monoxide is utilised as support for the silicon nitride, sothat the mechanical interactions between these two materials, that arein reciprocal contact during the annealing procedure, have beeninvestigated.

A further result achieved by this invention in that a capacitivetransducer cMUT of a new kind has been realised, comprising an array ofsuitably parallel to one another connected, electrostatic cells, havingan interelectrode spacing noticeably reduced with respect to the cMUTtransducers of the previous generations. This result has been madepossible by realising the lower metallisation of the device on the upperside of the starting substrate just under the cavities and themembranes, thereby enabling the distances between lower and upperelectrodes to be reduced by an amount substantially equal to thesubstrate thickness. In view of this reason, a novel technologic processhas been designed for manufacturing a transducer adapted to operate inmore efficient manner and at higher frequencies as well as with reducedparasitic capacitances in comparison to previously realised devices.

As an example of design flexibility offered by this technology, thepossibility to realise electrostatic cells having even relatively largedimension, aimed at realising a single array with components ofdifferent dimensions is to be mentioned. This technique enables to carryout a simultaneous scanning operations on layers arranged at differentdepths as well as the three-dimensional reconstruction in real time ofthe ecographic image, even if the application of the transducersaccording to this invention is not exclusively restricted to this field.

This invention will be now described by way of illustration, not by wayof limitation, according to its preferred embodiments, by particularlyreferring to the Figures of the annexed drawings, in which:

FIGS. 1A–1H and 1J–1N show the steps carried out in a first preferredembodiment of the method according to this invention;

FIGS. 2A–2F show six mask typologies as utilised for definition of themembranes in the process according to FIGS. 1A–1H and 1J–1N;

FIG. 3 is an upper plan view of the silicon semiconductor substrate asutilised in the process according to FIGS. 1A–1H and 1J–1N;

FIG. 4 is a three-dimensional view of a detail of FIGS. 1E and 1F;

FIG. 5 is an upper plan view and a cross-section view of the detail ofFIG. 4;

FIG. 6 is a three-dimensional view of the detail of FIG. 4 afterchemical treatment;

FIG. 7 is an upper plan view and a cross-section view of the detail FIG.6;

FIGS. 8A–8C show the steps carried out in stage B of a second preferredembodiments of the process according to this invention;

FIG. 9 shows a diagram graphically representing the compression stressof the membranes manufactured by the process according to thisinvention;

FIG. 10 shows a diagram graphically representing the absorption spectrumof the membranes manufactured by the process according to thisinvention;

FIG. 11 is a three-dimensional view of a membrane manufactured by theprocess according to this invention;

FIG. 12 is an upper plan view and a cross-section view of the membraneof FIG. 11;

FIG. 13 is an upper plan view and a cross-section view of a membranemanufactured by the process according to this invention at threesuccessive times;

FIG. 14 shows a microcell of the transducer manufactured by a thirdembodiment of the manufacturing process according according to thisinvention;

FIGS. 15A–15H and 15J–15N show the steps carried out in a thirdpreferred embodiments of the process according to this invention;

FIG. 16A shows a first pattern utilised for realising the lowermetallisations in the process according to FIGS. 15A–15H and 15J–15N;

FIG. 16B shows an enlarged portion of the pattern of FIG. 16A;

FIG. 17A shows a second pattern utilised for realising the lowermetallisations in the process according to FIGS. 15A–15H and 15J–15N;

FIG. 17B shows an enlarged portion of the pattern of FIG. 17A;

FIGS. 18A–18E show images of first intermediate products obtained duringthe process of FIGS. 15A–15H and 15J–15N as observed by an opticalmicroscope;

FIGS. 19A–19E show images of second intermediate products obtainedduring the process of FIGS. 15A–15H and 15J–15N as observed by anoptical microscope;

FIGS. 20A–20D show the images of a device realised by the process ofFIGS. 15A–15H and 15J–15N as observed by an optic microscope;

FIGS. 21 and 22 show a view of the AFM of a membrane manufactured by theprocess according to FIGS. 15A–15H and 15J–15N at two successive times.

In the following description, the same reference numerals will be usedto designate the same elements in the Figures.

In a first preferred embodiment of the process according to thisinvention, 340 devices corresponding to twelve different geometries aremanufactured on a single wafer. The realisation of a so large number ofdevices per wafer is possible in view of the fact that each device has asurface area of only 3 mm².

The circular shape of each individual electrostatic cell has beenselected since this shape optimises the characteristics of the generatedacoustic ultrasonic filed to the best.

In Table 1, the main geometrical characteristics of the twelve realisedtypologies are shown.

The process according to this invention starts from a silicon wafergrown according to the Czochralski methods, or CZ silicon, p-type dopedwith boron (density: 10¹⁷ cm⁻³), having a resistivity of about 0.1 Ω.cmwith crystallographic orientation <100>. The side of the wafer on heprocess is carried out is lapped.

TABLE 1 Rail minimum Number of Membrane Diameter of dimension Membranesdiameter Type of vias vias Type (10⁻⁶ m) per device (10⁻⁶ m) arrangement(10⁻⁶ m) 1 10 1512 40 A 6 2 10 1512 40 B 4 3 10 1512 40 C 8 4 10 1512 40D 4 5 10 1512 40 E 4 6 10 1512 40 F 4 7 10 1512 50 A 6 8 10 1512 50 B 49 10 1512 50 C 8 10 10 1512 50 D 4 11 10 1512 50 E 4 12 10 1512 50 F 4

The first step to be carried out is the application of a polyamide layerwhich will subsequently suitably etched in order to realise the layoutthat should receive the support rails of the structural layer. Thepolyamide layer forms the sacrificial layer and its thickness identifiesthe distance by which the membrane will be spaced from the substrateupon being released therefrom.

In particular, the polyamide represents the end treatment stage of amonomer solution that is applied to the wafer by means of a high speedcentrifugation technique or spinning. Two successive thermal treatmentsare subsequently carried out in order to promote the polymerisationreaction which results into a product designated as polyamide.

The thickness of the layer depends on the rotation speed and decreasesafter the polymerisation process is completed.

The polyamide utilised herein (N-methyl-2-pyrrolidone) is a polymermanufactured by Olin Microelectronic Materials having trade nameProbimide 112A selfpriming cat 851089.

The preliminary treatment of the wafer comprises a cleaning step toremove the atmospheric dust, performed by putting the wafer under a jetof deionised running water and then drying it by a jet of nitrogen. Moreadherent particles are removed by imaging the sample into an acetonebath in a tank run through by ultrasonic waves, in order to exploit thecavitation effect. A cleaning operation particularly aimed at removal oforganic residuals and fat acids can be carried out by immersion into abath formed by a solution comprising 70% sulphuric acid (H₂SO₄) and 30%hydrogen peroxide (H₂O₂).

After rinsing and drying the sample, a last dry cleaning step can becarried out by utilising oxygen plasma.

All water residuals, which could jeopardise the adhesion of the polymerto the surface, could be removed by means of a drying step carried outby heating the wafer in a furnace at 150° C. for 20 minutes.

The wafer in then arranged on the circular plate which the spinner isprovided with, about 3 ml polyamide are put at the central area of theplate and this plate is then rotated, initially at low speed, until thepolyamide reaches the edge of the wafer, then speed is increased up to4000 rpm during a total time of 120 seconds. The so prepared wafer isthen treated in a furnace at a temperature of 120° C. for 30 minutes, inorder to evaporate the solvents having the monomers dissolved therein.The last preparation stage of the layer to be subsequently utilised as asacrificial layer consists in the polymerisation process. The sample isarranged upon a quartz support in horizontal position within a metalwall furnace, immersed in a nitrogen flow. The thickness measured afterthe polymerisation stage is about 890 nm, which is higher than the 500nm limit as required by the specifications of the preferred embodimentof the process. A thinning stage should subsequently be carried out bymeans of a dry etching operation in RIE with a CF₄ flow rate of 12.6sccm (standard cubic centimetres per minute), an O₂ flow rate of 60sccm, under a pressure of 5.3 Pa, a power of 100 W and a via voltage of200 V: the removal rate is found to be 2.5 nm/s.

The lower electrode of the reactor should be protected by means of alarge silicon wafer, because it enables a higher etching spatialuniformity to be achieved. The etching time is of about 150 s.

The product obtained at the end of the above operations is shown in FIG.1A where the substrate 1 and the polyamide layer 2 cm can be observed.

The pre-patterning operations consist in etching the polyamide layer 2in order to form islands corresponding to the membranes that form thesacrificial layer. The etching procedure is carried out as a dry etchingoperation in a suitable plasma, by utilising an optical resist as amasking layer. A positive photolithographic process is utilised in orderto define the areas to be etched away in the polyamide film.

The mask utilised in the optical lithographic process is realised bymeans of an electronic lithographic process. It is possible to realiseon the same mask six different device typologies in respect of the viaarrangement, as it is shown in FIGS. 2A–2F.

The typology of FIG. 2A is designed to realise a single via for eachmembrane 3 at its centre area and it is almost designed to manufacture aprocess control device. The other typologies provide for realising thevias outside the circular membrane 3, in order to disturb the circulargeometry to the minimum possible extent. As regards the typologies shownin FIGS. 2B, 2D and 2E, the vias are positioned within the outwardlyprotruding lunettes 4. In the typology of FIG. 2F the vias should bearranged in order to be superimposed on the thin channels 5 protrudingfrom membrane 3.

The typology of FIG. 2C provides for arranging the vias 6 completelyoutwardly of membrane 3 and the chemical etch of the sacrificial layerreaches the area corresponding to membrane 3, namely the air gap,through the connection channels 7. This geometry in addition to beingscarcely perturbative enables optimum results to be obtainedparticularly at the stage in which the vias are to be closed, since thefilling of the vias is not critic to membrane vibration, because it issufficiently spaced apart and not tangent as in the other typologies.

A frame for separating the 340 transducers has been realised in order toaid performing the final cutting operations. The frame layout is shownin FIG. 3, where the devices with membranes of 40 μm diameter have beenrealised in the upper half section, while the devices with membranes of50 μm diameter have been realised in the layer half section.

At the end of the pre-patterning stage, polyamide islands having theshapes illustrated in FIGS. 2A–2F are obtained. By referring to FIG. 1B,polyamide islands 8 can be observed, such islands being protected byoptical resist masks 9, between which the layout 10 that will be filledby rails of silicon monoxide has been etched. The etching operation ofthe polyamide takes place in RIE in order to obtain a more verticalremoval with respect to the wet etching operations. The etchingoperation is carried out with a formulation as already defined inconnection with the thinning stage of the polyamide.

The etching time for removing 480 nm of polyamide is of about 156 s andit should be carefully controlled, because this formulation entails asilicon removal and, therefore, the risk to etch the substrate is run.The thickness control is effected by means of a profilometer. Theoptical resist masks 9 are not removed.

The rails are realised by thermally evaporated silicon oxide. The choiceof this material is suggested by the fact that, since a material is tobe deposited upon the optical resist in view of the subsequent lift offstep, it is necessary to carry out a low temperature process in view ofthe scarce heat resistance of such material. No particular treatment ofthe wafer is carried out before evaporation of the silicon oxide,besides the usual removal operation of the dust particles in deionisedwater and in nitrogen flow. The thickness of the evaporated siliconoxide depends on the polyamide thickness existing on the sample, becauseboth the oxide and the polyamide are to be levelled in order to obtainas much planar membranes as possible. The deposited thickness is equalto 500 nm.

After this stage is completed, the situation is as shown in FIG. 1C, inwhich the rails 11 of silicon monoxide and the silicon monoxide areas 12overlapping the optical resist masks 9 are shown.

The subsequent step provides for removing the silicon monoxide areas 12.The sample is immersed in acetone in order to dissolve the resist masks9 by removing then the superimposed monoxide areas 12.

The amount of silicon monoxide to be removed is noticeable and,therefore, a good resist dissolution efficiency is necessary. A detailof FIG. 1C is shown in FIG. 1D to evidence that etching of resist byacetone starts from side direction. Therefore, it is necessary that thethickness of said resist masks 9 be sufficient, in respect of themonoxide amount to be evaporated, not to allow the side of said masks 9to be covered. However, should the vertical side of the concerned resistbe completely covered by monoxide, it would anyway be possible to removeit by other techniques.

After a few minutes of treatment with acetone, possibly with ultrasonicaid, the situation shown in FIG. 1E is reached.

The enlargement illustrated in FIG. 1F shows the unavoidable monoxideresidual 13, also called “bind wing”, remaining at themonoxide-polyamide interface. This is a typical secondary effect of thistechnique and it is undesired in view of the fact that it represents abreakage point for the membrane to be superimposed to it.

FIG. 4 illustrates the three-dimensional reconstruction of themonoxide-polyamide interface profile based upon a surface scan obtainedby means of an atomic force microscope or AFM.

FIG. 5 illustrates the cross-section of the same profile and themeasurement of the differences in height existing between the polyamideisland 8, the monoxide rail 11 and monoxide residual 13.

Aiming at reducing the defects existing at the edges, it is suggested tooperate with a wet etching operation in 5% solution of hydrogen fluoride(HF). The immersion time is very short, about 2 s, because the siliconmonoxide forming the rail member 11 should not be etched away.

Aiming at protecting the polyamide in respect of the hydrogen fluoride,the immersion is performed before carrying out the lift off operation bymeans of an acetone bath, in order that the resist layer and the siliconoxide protect the underlying polyamide. This measure further improvesthe resist dissolution rate and accuracy in the subsequent acetone bath,because the vertical sides will be more exposed to the etching solution.

By referring to FIG. 6, it can be observed that the wet etchingoperation nearly completely eliminates the bind wing formation 13, butit generates a groove 14 caused by penetration of the hydrogen fluorideto the monoxide-polyamide interface.

As it is shown in FIG. 7, the depth of the groove is not amenable toraise problems because the 500 nanometres of silicon nitride to bedeposited thereon will be sufficient to fill it up.

The drawback caused by said groove is overcome in a second preferredembodiment of this invention, in which the stage providing forrealisation of the intermediate product comprising polyamide islands 8and silicon monoxide rails 11 is different from the one described byreferring to FIGS. 1A–1E. By referring to FIGS. 8A–8C, it can beobserved that said rails 11 are deposited before depositing saidsacrificial polyamide, by means of a carpet deposition process extendedto the whole wafer, followed by pattern definition by means of a plasmaetching operation (FIG. 8A). Polyamide is subsequently deposited tocover the wafer (FIG. 8B) the liquid phase deposition and the subsequentpolymerisation or curing operation make the surface profile gradual, butsill sufficiently conforming to the underlying topography relating tothe monoxide rails 11. Lastly, a planarisation step is carried out bymeans of a chemical-mechanical polishing operation, by utilising asilica particle solution in alkaline environment, by rubbing the waferagainst a hard surface, preferably a glass surface. The surface turnsout to be completely planarised at the end of the polishing procedure,without formation of grooves at the edges of the rails 11 (FIG. 8C).

By referring to FIG. 1G, it can be observed that layer 15, by which saidmembranes are formed, is realised by silicon nitride deposited byutilising a PECVD reactor. The thickness of the deposited film is ofabout 500 nm. A good adhesion is achieved between the silicon nitrideand the monoxide. A preliminary cleaning operation is carried out inacetone for 300 s followed by rinsing in deionised water.

In comparison to films grown by a LPCVD procedure, a PECVD procedureenables films to be deposited at low temperatures, lower than 400° C.,and with mechanical characteristics variable within an extended range.The deposition of films of high quality at low temperatures allows toutilise, for the sacrificial layer, materials that can be removed veryrapidly and with very high selectivity in respect of silicon nitride,such as polyamide or optical resist.

The control of the growing parameters of the silicon nitride films isessential for the obtainment of efficient membranes.

Laboratory tests have evidenced the problem of the mechanicalcompression stress of the silicon nitride films grown by means of aPECVD reactor. It was not possible to directly grow a silicon nitridefilm affected by tensile stress. The growing parameters adapted tominimise the compression stress are shown in Table 2.

TABLE 2 RF Frequency 13.56 MHz Power 10 W Temperature 650 K Pressure 70Pa Silane flow 11 sccm Nitrogen flow 170 sccm Helium flow 220 Sccm

FIG. 9 shows a diagram of the compression stress behaviour as a functionof the silane/nitrogen ratio according to the measurements affected.

When the flow rate of silane is decreased with respect to the flow rateof nitrogen, a reduction of the compression stress can be observed. Thelarge amount of nitrogen in the film, however, makes the film morefragile.

The mechanical stress in the membranes can be modified by means of heattreatments carried out after the film deposition. Heating the siliconnitride to temperatures higher than 500° C. causes thickening of thefilm due to hydrogen desorption with formation of linkages betweensilicon and nitrogen. The reduction of the linkages Si—H (about 2100cm⁻¹) clearly appears from the absorption spectrum of FIG. 10. Thisspectrum is obtained by infrared spectroscopy or FTI, and it resultsfrom subtraction of the absorption of a silicon sample with 400 nmnitride and of the absorption of a clean silicon sample. The noiseencountered in connection with wave numbers higher than 2200 cm⁻¹ is dueto variations in air absorption between the acquisitions.

By referring to FIG. 1H, the holes through which the etching operationof the silicon nitride is carried out by means of a RIE etchingprocedure, aimed at realising the vias 16, are defined by a subsequentlithographic operation. In particular, the etching operation is carriedout with a CHF₃ flow rate of 50 sccm, an O₂ flow rate of 8 sccm, apressure of 7.1 Pa, a power of 180W and a bias voltage of 260 V: theremoval rate of the silicon nitride 15 turns out to be 0.67 nm/s, whilethe removal rate of the optical resist 17 is of 0.5 nm/s.

The etching time to realise a through hole in a standard membrane of 500nm is of about 600 s, but aiming at assuring that said vias 16 reach thesacrificial layer 8, such duration is extended to 900 s, without causingany damage, also keeping in mind that said sacrificial layer will beeventually removed.

It is subsequently proceeded to a membrane releasing step. By referringto FIG. 1J, at the end of the polyamide sacrificial layer 8 removal, thesilicon nitride membranes 18 are suspended on an air gap 19 of 500 nmand are sustained by rails 11 of silicon monoxide. The chemical etchingstep on the polyamide is carried out preferably by immersion in a 7:3solution of sulphuric acid (H₂SO₄) and hydrogen peroxide (H₂O₂) thatstrongly attacks any compound, particularly the polyamide, by means of ahighly exothermal reaction, rapidly reaching 353K. The selectivity inrespect of silicon nitride, silicon oxide and silicon itself amounts to100%.

The complete removal of the sacrificial layer is carried out in just2400 s time and the 100% selectivity assures a perfect integrity of thesilicon oxide and silicon nitride films.

Should no heat treatment be carried out, the intrinsic compressionstress under which the PECVD nitride grows immediately appears onreleasing the membranes. The effect observed is a camber in the membranedue to the fact that the silicon nitride film has a tendency toincreasing its surface and the membranes engaged with the rail have atendency to explode upwardly. The circular geometry of the cells, thearrangement of the holes, the dimensions of the membranes and thetreatments carried out after the lift off operation synergisticallycontribute not to fragment the membrane even under a compression stress.FIG. 11 shows the three-dimensional reconstruction effected by said AFMfor a membrane according to typology of FIG. 2C, subjected to acompression stress after release, which makes it cambered upwardly.

FIG. 12 shows the cross-section of the membrane of FIG. 11: the camberof the membrane is of about 1 nm which, when compared to 40 nm diameterof the membrane, does not appear to be so relevant. Anyway, in view ofassuring a correct operation of the transducer, a tensile stress appearsto be preferable with respect to a compression stress.

When membranes having a higher Young's modulus are desired, byincreasing the silicon amount contained in the nitride film, an increasein the compression stress is obtained, which could cause breakage ofmany membranes.

In the preferred embodiment of the process according to this invention,the stress is gradually relieved by means of thermal treatments in whichthe sample is heated to a temperature in the range of 490° C. to 530°C., preferably a temperature equal to 510° C.

FIG. 13 shows the variation of the membrane profile achieved bysubjecting the concerned device to two thermal annealing treatments,each extended to a 5 hour duration. The first annealing treatment iscarried out before the removal of the polyamide sacrificial layer,thereby reducing the compression stress and also making it notdestructive during the release step of the membranes.

In particular, the duration of the first thermal treatment can be suchas to completely consume the polyamide material, thereby making theremoval to be effected by chemical etching redundant. Further thermaltreatments can be carried out in order to further reduce the intrinsiccompression stress and to introduce an intrinsic tension stress intomembranes.

Furthermore, the annealing treatments allow to achieve a very highdesign flexibility, also in terms of geometry and dimensions of themembranes.

After release of the membranes, the vias can be closed by means of asilicon monoxide deposition, having a thickness equal to the thicknessof the air gap 19, and of an optical lithography operation. Lastly, ametallisation of both sides of the wafer is carried out.

By referring now to FIG. 1K, it can be observed that the closure of thevias takes place as a column filling thereof by utilising siliconmonoxide that forms the stoppers 22. The thickness of the monoxide layer20 as deposited ought to be sufficient to form stoppers 22 reaching theunderlying nitride 18. In view of the above, it is necessary to depositat least a thickness equal to the air gap 19, which means 500 nm, in thepreferred embodiment, and, obviously a higher thickness is usuallydeposited for safety reasons, equal to 700 nm. The deposition techniqueis a low temperature evaporation based upon heating by Joule's effect acrucible containing silicon monoxide grains.

By referring to FIG. 1L, the monoxide layer 20 deposited on membranes 18should be removed because otherwise it would not allow a correctoperation of the transducer. The removal is carried out by means of anoptical lithographic operation with subsequent etching operation in RIE.The optical lithographic procedure is needed because it is. necessary tocreate a mask layer 21 consisting of an optical resist, suitably shapedin order to protect said stoppers 22 from the etching agent acting onthe silicon monoxide, leaving the monoxide 20 superimposed to themembrane 18 exposed. Preferably, the thickness of the resist is 1.5 nm.Etching of the silicon monoxide is carried out in RIE according to theformulation already discussed in respect of the etching operationperformed on silicon nitride for realising the vias. It is necessary toremove 700 nm of silicon oxide and, therefore, considering that theetching rate is of about 0.8 nm/s, the etching time is of about 875seconds. The utilised formulation slowly removes also said opticalresist, but this does not raise any problem, because it has a endurancewell beyond the duration of the etching operation.

The utilised formulation is not selective in respect of the underlyingsilicon nitride, so that, during the etching operation, it is necessaryto control the oxide removal status, in order to stop the procedure assoon as it is finished.

Subsequently, the residual resist is removed by an oxygen plasma in RIE,under an O₂ flow rate equal to 67 sccm, a pressure equal to 5.3 Pa, apower equal to 100 W and a bias voltage equal to 200 V. Alternatively,the sample can be immersed in acetone for a few minutes and then rinsedin deionised water. At the end of the resist removal operation, theproduct shown in FIG. 1M is obtained.

Should it be desired to make the electric control of the transducerpossible, it will be necessary to metallise the membranes 18 and theback surface of the wafer 1.

By referring to FIG. 1N, the back surface of the wafer is metallised bydeposition of an aluminium film 23 of 150 nm thickness. The surface tobe metallised is of not-lapped silicon. Such surface should be cleanedand not oxidised, in order to guarantee a good adhesion of the film aswell as a good ohmic contact. At the end of the process, the wafer isheated to 650K for 1800 seconds in order to improve the ohmic contact,in a steel furnace, under a nitrogen flow rate of 30 sccm.

On the other side of the wafer 1, aiming at reducing the parasiticcapacitances of the transducer, only membranes 18 are metallised. Onlyconnections between the electrodes are provided corresponding to therails 11, while the contact with the external circuit is realised bymeans of a suitable pad. The metallisation pattern is realised by meansof an optical lithographic process, with utilisation of a mask realisedby an electronic lithographic process. The aluminium film applied formetallisation of the membranes is deposited by sputtering. The metallayer patterning operation is carried out by means of a further opticallithographic process, with utilisation of a mask realised by means of anelectronic lithographic process, thereby obtaining the metallisationareas 24 of the membranes 18.

In a third embodiments of the process according to this invention, byreferring to FIG. 14 to 22, the main improvements are connected withutilisation of new materials to realise the lower metallisation and thesacrificial islands of the transducer.

For realisation of the lower electrodes, it is suggested to utilisechromium as conductive material rather than aluminium, as alwaysutilised in the prior art devices, even if chromium has a resistivity of12.7×10⁻⁸ Ω.m. Such choice is determined by the fact that aluminium isnot adapted to withstand the deposition temperatures of the subsequentlayers which the device consists of. Furthermore, aiming at reducing theparasitic capacitances established in the transducer, the chromium layeras deposited is suitably patterned by means of an optical lithographicprocess, in order to obtain a structure exclusively entailing themetallisation of a restricted area corresponding to the cavities orhollow chambers and to the membranes. The upper metallisation isrealised by deposition of an aluminium layer, rather than chromium, inview of the fact that the latter would grow with a highly tensilemechanical stress, which sometimes could be destructive for themembranes. The aluminium film is subsequently treated in order to definethe metallised areas on the membranes and their interconnections,positioned with a complementary configuration with respect to theinterconnections of the lower metallisation, in order to limit theincidence of parasitic capacitances.

Another noticeable improvement is related to utilisation of chromium assacrificial material in substitution for the most common siliconcompounds. The chemical etching operation utilised for its removal has aselectivity of 100% in respect of the other materials utilised therein,such as the silicon nitride, the silicon monoxide and the siliconitself, thereby assuring a perfect control of the active region of thetransducer. In this way, the materials by which the device will beeffectively formed are in no way deteriorated, thereby maintaining alltheir performances in respect of resistance and density. In fact, as ithas been already evidenced, should a material having a low etchingselectivity level with respect to the structural layers be utilised,also the membranes and the walls would be etched during removal of thesacrificial material, thereby modifying the dimensions of the cells andthe thickness of the membranes themselves, with resulting variation ofthe characteristic properties of the transducer.

Also in this third preferred embodiment, the pre-patterning technique isexploited by defining, by means of a photolithographic procedure, thesacrificial islands before deposition of the membranes, in order toguarantee a micrometric definition of the device geometry. The hollowchambers or cavities upon which the membranes are suspended effectivelyrepresent the active regions of the transducer. Their geometry anddimension represent the main factors by which the performances of thedevice are characterised.

In particular, FIG. 14 shows a microcell of the transducer manufacturedby means of the third embodiment of the manufacturing process accordingto this invention. In this case, the lower metallisation 25 is directlyrealised on the upper surface of the wafer, just under the membranes 18and the corresponding cavities, thereby reducing the distance betweenstationary lower electrodes and the mobile upper electrodes by athickness substantially equal to the thickness of substrate 1, equal toabout 380 nm.

The third embodiment of the manufacturing process according to theinvention utilises 3″ p-type doped silicon wafers, having a resistivityof about 0.1 Ω.cm with crystallographic orientation <100>.

A number of 340 devices are micromachined on a single wafer, each ofwhich is characterised by 1512 membranes. A so high number of devices ismade possible by the small area engaged by each of them equal to 3 mm².Each membrane has a circular type shape realised by referring topolygons of 16 sides. Such a geometry perfectly matches thecharacteristics of the acoustic field generated. The individualmembranes appear to be arranged according to a configuration of amatricial type with a minimum distance of 10 nm from one another.

One half of the devices realised on the wafer are formed by membraneseach having a diameter of 40 nm, while the devices of the other half areformed by membranes having a greater diameter equal to 50 nm.

As far as each device is concerned, reference is made to electrostaticcells having geometric shapes realised, in respect of the holes providedfor etching the sacrificial layer and the connection bars, according tothe five different typologies shown in FIGS. 2B, 2C, 2D, 2E and 2F. Intotal there are ten different typologies realised by exploiting the twodifferent dimensions of the considered membranes.

By referring to FIG. 15A, according to the third embodiment of theprocess of this invention, an insulating layer 26 of thermal silicondioxide SiO₂ is deposited to isolate the starting silicon substrate 1from the lower metallisation.

By referring to FIG. 15B, the process provides for realising the lowerelectrodes 25. The lower metallisation is realised by depositing auniform chromium layer by evaporation. The chromium film is subsequentlypatterned by means of an electronic lithographic process aimed atimparting a particular geometric shape to the lower metallisation. Theneed to reduce the parasitic capacitances of the transducer resultedinto metallisation of the membranes 18 only so that the connectionsbetween the electrodes 25 are realised by means of suitable conductivepaths realised in positions corresponding to the rails 11 and thethickness of which is not higher than 4 nm. The dimensions of theelectrodes 25 are selected to optimise the performances of thetransducer. They are exclusively realised in the central portion of eachmembrane 18 so as to increase the ratio between the capacitancemodulation and the static capacitance of the device. Due to this reason,the process realises electrodes 25 utilising only 60% of a surfacecorresponding to the surface of the membranes 18 and with a smallthickness if compared to the thickness of the membranes 18. Whenmembranes 18 having diameters of 40 μm and 50 μm are realised, theobtained electrodes 25 have diameters of 24 μm and 30 μm, respectively.

Connection pads are utilised to allow the realisation of an electriccontact between the electrodes 25 and the external circuit.

As it is shown in FIG. 15C, the pattern of the lower electrodes 25 andof their related interconnections is protected by means of a film 27 ofsilicon nitride SiN grown by means of a PECVD technique.

Subsequently, as it is shown in FIG. 15D, a film 28 of chromium isdeposited by means of an evaporation technique as a sacrificialmaterial.

By referring to FIG. 15E, pre-patterning of sacrificial islands 8′ iscarried out by means of an optical lithographic process, by utilising asuitable mask realised by means of an electronic lithographic process. Asubsequent wet etching operation is carried out on said chromium inorder to define the regions forming said island 8′. The chromium layerexclusively remains unaltered in regions corresponding to the area bywhich the cavities (air gap) of the transducer will be characterised.The above said layer 28 defines the thickness of the cavity in thetransducer and, therefore, it is a critical variable in designing theperformances of the transducers. The resist (not shown) applied upon theislands 8′, which is not exposed during the lithographic process, is notremoved in order to permit execution of the subsequent step of theprocess.

In particular, FIG. 18A, 18B, 18C and 18E show the optical microscopeimages of the chromium sacrificial islands 8′ before the monoxide rails11 are formed, respectively corresponding to the five geometric shapesof the etching holes shown in FIGS. 2B, 2C, 2D, 2E and 2F.

By referring now to FIG. 15F, a layer of silicon monoxide SiO, isdeposited by means of an evaporation operation based upon the Joule'seffect, in order to realise a planar type structure and to create rails11 aimed at supporting the membranes 18. The excess monoxide grown uponthe islands 8′ is removed by means of a lift off process, by dissolvingthe resist not removed by the previous step, by acetone and ultrasounds.

The thickness of the deposited monoxide is equal to the thickness of thesacrificial islands 8′ in order to obtain rails 11 having the sameheight as the cavities. This enables a subsequent structural layer ofthe membranes 18 to be deposited upon a planar type surface, therebyassuring a uniform stress distribution in the membranes and avoidingpossible breakage points for the membranes themselves.

In particular, FIGS. 19A, 19B, 19C, 19D and 19E show the opticalmicroscope images of the chromium sacrificial islands 8′ after themonoxide rails 11 have been created, respectively corresponding to thefive geometric shapes of the etching holes shown in FIGS. 2B, 2C, 2D, 2Eand 2F.

By referring to FIG. 15G, the realisation of the membranes 18 is carriedout by depositing a layer 15 of silicon nitride SiN_(x) by exploiting aPECVD technique. The residual stress of the nitride film 15 can becontrolled by varying the plasma frequency, the substrate 1 temperatureand the nitrogen and silicon relative concentrations during thedeposition process. The intrinsic stress in the silicon nitride membrane18 has been designed so as to have a scarce tensile character bycontrolling the radio-frequency power in the PECVD process. Thethickness of the film 15 can be controlled in the PECVD process, aswell. The stress under which the film 15 is grown represents anessentially important factor in view of the fact that, as previouslydiscussed, the resonance frequency of the membrane 18 depends thereon.

A thermal annealing step of the sample is then carried out in order toreduce the compression stress in the membranes 18, which would cause asubsequent camber effect as well as their breakage after releasingthereof, with conversion of the compressive stress into a weakly tensilestress.

By referring to FIG. 15H, it can be observed that submicrometricapertures 16 (etchant holes) are defined, by means of an opticallithographic process, on the membrane 18 area, in order to enablechromium to be subsequently removed from the underlying sacrificialislands 8′. The above mentioned apertures 16 are provided in perimetralpositions on each individual membrane according to five differenttypologies as shown in FIGS. 2B–2F, which assure an efficient etching ofsaid sacrificial islands 8′ as well as an excellent mechanical stabilityof the structure.

A mask with a pattern of holes 16 having a design diameter of 4 nm isrealised by means of an electronic beam lithographic process. Thedimensions of the vias 16 should be small, in order to enable the holesto be closed and the cavities be sealed, but, on the other hand, theyshould be sufficiently large as to enable the underlying sacrificiallayer to be removed.

The realisation of said silicon nitride vias 16 is carried out on thesilicon by means of a dry etching operation with a reactive ion etching(RIE) technique.

By referring to FIG. 15H, it can be observed that, upon opening the vias16 through the nitride layer 15, the sacrificial chromium layer 8′ isremoved by means of a suitable wet etching solution. This etchingoperation is isotropic and assures a 100% selectivity in respect of thestructural nitride and the monoxide SiO of rails 11. The above solutionpenetrates through holes 16 and removes the chromium underlying themembranes 18, thereby having them in suspended condition.

As it is shown in FIG. 15J, the product at this point consists of amatrix of silicon nitride membranes 18 suspended on silicon monoxidesupports 11.

By referring to FIG. 15K, it can be observed that, upon releasing saidmembranes 18, the above vias 16 are closed by two successive steps: asilicon monoxide SiO deposition by means of an evaporation operationbased upon the Joule's effect, with a thickness equal to the thicknessof the cavities, and an optical lithographic step.

The vias 16 are closed by column filling them with the same material bywhich the rails 11 are formed. The thickness of the monoxide layer 20 asdeposited should be sufficient to form stoppers 22 extended up toreaching the overlying silicon nitride layer 18.

The removal of the monoxide layer 20 deposited on said membranes 18 iscarried out by means of an optical lithographic process and a dryetching operation in RIE, thereby obtaining the product shown in FIG.15L.

The optical lithographic step allows to realise a masking layer ofoptical resist so shaped as to protect the above said stoppers 22 inrespect of the etching step carried out on the silicon monoxide and toleave the monoxide overlying the membranes 18 uncovered, in similar wayas shown in FIG. 1L.

It is necessary that said etchant holes 16 be closed, not only in orderto enable the concerned transducers to be utilised in immersedcondition, but also to protect the cavities from possible contaminationsthat could modify the vibration properties of said membranes 18, withresulting alteration of the performances of the concerned transducer.

Aiming at further improving the sealing of said vias 16, a thin film ofsilicon nitride SiN is preferably grown subsequently by means of PECVDtechnique, which enables hermetic sealing of said vias 16, withoutsignificantly modifying the vertical dimension of the transducer.

The subsequent process step is aimed at realising the uppermetallisation.

A conductive layer of aluminium is deposited by a sputtering operation.A subsequent deposition of a thin layer of titanium is then carried outalso by sputtering.

The pattern of the upper electrodes 24 and of the relatedinterconnections (not overlapping the lower interconnections) isrealised by means of an optical lithographic process, under utilisationof a mask realised by means of an electronic lithographic process.Aiming at reducing the parasitic capacitances of the transducer, onlysaid membranes 18 are metallised. Corresponding to rails 11 onlyconnections between electrodes 24 are provided in complementarypositions with respect to the connection paths of the electrodes 25 ofthe lower metallisation, in order to avoid useless overlaps and toreduce any possibly existing parasitic capacitances. The contact to theexternal circuitry occurs by means of a suitable pad.

The titanium layer in the exposed regions of the optical resist is thenremoved by means of a dry etching operation in RIE. The underlyingexposed aluminium layer is removed by a wet etching operation in asuitable etchant solution, thereby obtaining the product shown in FIG.15M.

In particular, the pads corresponding to the lower metallisation areopened by means of a lithographic process with related mask and by meansof a dry etching operation in RIE aimed at removing the structuresilicon nitride SiN_(x) and the silicon monoxide layers.

By referring to FIG. 15N, the wafer is then covered by a thin protectionlayer 28 of silicon nitride SiN_(x) grown by means of a PECVD technique,utilised for protecting the upper metallisation and to assure hermeticsealing of the cavities.

The pads are opened in order to enable the realisation of the contactsto the measurement external circuitry, by means of an opticallithographic process, with utilisation of a mask realised by means of anelectronic lithographic process and a dry etching operation in RIE, forremoval of the protection silicon nitride SiN_(x) corresponding to thelower and upper pads.

In particular, FIG. 16A shows a first configuration as utilised for thelower metallisation clearly evidencing pad 29 for connection to theexternal circuitry. FIG. 16B shows an enlarged portion of theconfiguration of FIG. 16A.

In similar way, FIG. 17A shows a second configuration as utilised forthe lower metallisation, and FIG. 17B shows an enlarged portion thereof.

FIGS. 20A, 20B, 20C and 20D show optical microscope images of thefinished device, clearly evidencing the membranes 18, the rails 11, theetchant vias 16 and the lower electrodes 25 and upper electrodes 24.

FIG. 21 is an AFM view of a membrane 18 before the thermal annealingstep, while FIG. 22 is an AFM of the same membrane 18 after the thermalannealing step.

The preferred embodiments of this invention have been described and anumber of variations have been suggested hereinbefore, but it shouldexpressly be understood that those skilled in the art can make othervariations and changes, without so departing from the scope thereof, asdefined by the enclosed claims.

1. A surface micromachining process for manufacturing Electroacoustictransducers, particularly ultrasonic transducers, said transducerscomprising a silicon semiconductor substrate (1), on an upper surface ofwhich one or more membranes (18) of resilient materials are supported bya structural layer (11) of insulating material, rigidly connected tosaid silicon semiconductor substrate (1), said resilient material havinga Young's modulus not lower than 50 GPa, said membranes (18) beingmetallised, said transducers including one or more lower electrodes (23,25), rigidly connected to said silicon semiconductor substrate (1), theprocess comprising the following steps: A. providing said siliconsemiconductor substrate (1), B. realising an intermediate productcomprising: a sacrificial layer (8, 8′), and a structural layer (11) ofinsulating material, rigidly connected to an upper surface of saidsilicon semiconductor substrate (1), the surfaces of said sacrificiallayer (8, 8′) and of said structural layer (11) not in contact with saidsilicon semiconductor substrate (1) being substantially co-planar, C.depositing a layer (15) of said resilient material on said sacrificiallayer (8, 8′) and on said structural layer (11), and D. releasing saidmembranes (18) of said resilient material by removing said sacrificiallayer (8, 8′) from the product obtained according to said step C., saidprocess being characterised in that said structural layer (11) includessilicon monoxide.
 2. A process according to claim 1, characterised inthat all of the steps of the process are carried out at temperatures nothigher than 600° C.
 3. A process according to claim 2, characterised inthat all of the steps of the process are carried out at temperatures nothigher than 530° C.
 4. A process according to claim 1, characterised inthat said resilient material has a value of the Young's modulus notlower than 100 GPa.
 5. A process according to claim 4, characterised inthat said resilient material comprises silicon nitride.
 6. A processaccording to claim 4, characterised in that said resilient materialcomprises crystalline silicon.
 7. A process according to claim 1,characterised in that said sacrificial material (8′) comprises chromium.8. A process according to claim 1, characterised in that saidsacrificial material (8) comprises an organic polymer selected among thegroup consisting of polyamides and polymers of benzocyclobutene and itsderivatives.
 9. A process according to claim 8, characterised in thatsaid organic polymer comprises polyamide.
 10. A process according toclaim 9, characterised in that said polyamide comprisesN-methyl-2-pyrolidone.
 11. A process according to claim 1, characterisedin that said step D comprises the following successively orderedsub-steps: D.1 realising one or more apertures or vias (16) on saidlayer (15) of resilient material, adapted to enable accessing thesacrificial layer (8) from outside, and D.2 thermally treating byannealing the product obtained according to said step C.
 12. A processaccording to claim 9, characterised in that, during execution of saidsubstep D.2, the product obtained according to said step C is heated toa temperature in the range of 490° C. to 530° C.
 13. A process accordingto claim 11, characterised in that said sub-step D.2 has a durationadapted to completely eliminate the organic polymer existing in theproduct obtained according to said step C.
 14. A process according toclaim 11, characterised in that said step D further comprises,indifferently before or after said sub-step D.1 or D.2, the followingsub-step: D.3 chemically etching said sacrificial layer.
 15. A processaccording to claim 14, characterised in that said sub-step D.3 comprisesimaging the product in a wet etching solution for etching chromium. 16.A process according to claim 14, characterised in that said sub-step D.3comprises imaging the product obtained according to said step C in asolution comprising sulphuric acid (H₂SO₄).
 17. A process according toclaim 16, characterised in that said solution utilised in said sub-stepD.3 further comprises hydrogen peroxide (H₂O₂).
 18. A process accordingto claim 17, characterised in that said solution utilised in saidsub-step D.3 is a solution 7:3 of sulphuric acid (H₂SO₄) and hydrogenperoxide (H₂O₂).
 19. A process according to claim 14, characterised inthat, when said sub-step D.3 is subsequent to said sub-step D.2, saidstep D further comprises, after said sub-step D.3, the followingsub-step: D.4 thermally treating by annealing the product obtainedaccording to said step D.
 20. A process according to claim 19,characterised in that, during execution of said sub-step D.4, theproduct obtained according to said step C is heated to a temperature inthe range of 490° C. to 530° C.
 21. A process according to claim 11,characterised in that the total duration of the annealing operation forthe product obtained according to said step C is adapted to make theintrinsic compression stress of the membranes (18) no higher than 10MPa.
 22. A process according to claim 21, characterised in that thetotal duration of the annealing operation for the product obtainedaccording to said step C is adapted to make the intrinsic tensile stressof the membranes (18) comprised in the range of 10 MPa to 50 MPa.
 23. Aprocess according to claim 11, characterised in that said vias (16) areexternal to the locations of said membranes (18) and are positioned at adistance therefrom adapted to introduce substantially negligible stressgradients, said sacrificial layer (8) comprising channels (7) to connectthe positions of said vias (16) to the locations of said membranes (18).24. A process according to claim 7, characterised in that said step Bcomprises the following successively ordered sub-steps: B.1 depositing achromium comprising layer (28) on said upper surface of said siliconsemiconductor substrate (1), B.2 defining configurations or patterns insaid chromium comprising layer (28) by realising cavities in saidchromium comprising layer (28), and B.3 filling said cavities in saidchromium comprising layer (28) by depositing silicon monoxide therein.25. A process according to claim 8, characterised in that said step Bcomprises the following successively ordered sub-steps: B.1 applying alayer (2) comprising said organic polymer upon said upper surface ofsaid silicon semiconductor substrate (1), B.2 defining configurations orpatterns in said layer (2) comprising said organic polymer by realisingcavities (10) in said in said layer comprising said organic polymer, andB.3 filling said cavities (10) in said layer (2) comprising said organicpolymer by depositing silicon monoxide therein.
 26. A process accordingto claim 24, characterised in that, during said sub-step B.3, thesilicon monoxide is deposited by thermal evaporation.
 27. A processaccording to claim 24, characterised in that said sub-step B.2 comprisesan optical lithographic process performed on said chromium comprisinglayer (28) by utilising a masking layer of photographically patternedoptical resist and a wet chemical etching of the chromium.
 28. A processaccording to claim 25, characterised in that said sub-step B.2 comprisesa dry reactive ion etching (RIE) operation performed on said layer (2)comprising said organic polymer by utilising a masking layer (9) ofphotolithographically patterned optical resist.
 29. A process accordingto claim 27, characterised in that said step B further comprises, aftersaid sub-step B.3, the following sub-steps: B.4 chemically etching saidsilicon monoxide by utilising a wet etching process, B.5 removing saidoptical resist.
 30. A process according to claim 27, characterised inthat said step B further comprises, after said sub-step B.3, thefollowing sub-step: B.4 removing the silicon monoxide deposited uponsaid optical resist by means of a lift off process.
 31. A processaccording to claim 30, characterised in that said sub-step B.4 comprisesdissolving said optical resist by means of an acetone and ultrasounddissolving process.
 32. A process according to claim 8, characterised inthat said step B comprises the following successively ordered sub-steps:B.1 depositing a silicon monoxide comprising layer on said upper surfaceof the semiconductor substrate (1), B.2 defining configurations orpatterns (11) in said silicon monoxide comprising layer, B.3 applying alayer (2) comprising said organic polymer upon said upper surface of thesemiconductor substrate (1), provided with silicon monoxide, B.4performing a chemical-mechanical polishing operation adapted to realisesaid intermediate product.
 33. A process according to claim 32,characterised in that during said sub-step B.1, the silicon monoxide isdeposited by thermal evaporation.
 34. A process according to claim 32,characterised in that said sub-step B.2 comprises a dry reactive ionetching (RIE) operation performed on said silicon monoxide comprisinglayer by utilising a masking layer of photolithographically patternedoptical resist.
 35. A process according to claim 1, characterised inthat, during said step C, said resilient material is deposited by aplasma enhanced chemical vapour deposition process (PECVD).
 36. Aprocess according to claim 11, characterised in that it furthercomprises, after said step D, the following step: E. closing said vias(16) by deposition of silicon monoxide adapted to fill up said vias(16), optical lithography, and RIE etching of the silicon monoxidedeposited on said membranes (18).
 37. A process according to claim 36,characterised in that during said step E, said silicon monoxide isdeposited by thermal evaporation.
 38. A process according to claim 1,characterised in that it further comprises, before said step B, thefollowing step: F. realising a lower electrode (25) on the upper surfaceof the semiconductor substrate (1) in positions corresponding to eacharea in which said membranes (18) are realised during said step D.
 39. Aprocess according to claim 38, characterised in that said step Fcomprises the following sub-steps: F.1 depositing an insulating layer(26) on the upper surface of the semiconductor substrate (1), F.2depositing a conductive layer upon said insulating layer (26), F.3defining configurations or patterns in said conductive layer.
 40. Aprocess according to claim 39, characterised in that said insulatinglayer (26) comprises thermal silicon dioxide SiO₂, said conductive layercomprises evaporation deposited chromium, and said sub-step F.3comprises an optical lithographic process performed on said conductivelayer by utilising a masking layer formed by a photolithographicallypatterned optical resist and a chemical wet etching of the chromium. 41.A process according to claim 38, characterised in that said step Ffurther realises a film (27) for protection of said lower electrodes(25).
 42. A process according to claim 41, characterised in that saidprotection film (27) is realised by growing a film of silicon nitridesIN by means of a PECVD technique.
 43. A process according to claim 1,characterised in that it further comprises the following step: F.realising one or more lower electrodes (23) by metallisation of a lowersurface of said siliconsemiconductor substrate (1).
 44. A processaccording to claim 1, characterised in that it further comprises thefollowing step: G. metallising said membranes (18).
 45. A processaccording to claim 1, characterised in that said silicon semiconductorsubstrate (1) is a p-type doped silicon substrate having a resistivityno higher than 1 Ω.cm, preferably no higher than 2 Ω.cm.
 46. A processaccording to claim 1, characterised in that said silicon monoxidecomprising structural layer (11) has a thickness in the range of 100 nmto 1000 nm, preferably in the range of 400 nm to 600 nm, and in thatsaid membranes (18) of said resilient material have a thickness nohigher than 1000 nm, preferably no higher than 600 nm.